? semiconductor components industries, llc, 2016 june, 2016 ? rev. p1 1 publication order number: NCP81063/d NCP81063 product preview synchronous buck mosfet drivers the NCP81063 is a high?performance dual mosfet gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. a zero?current detection feature allows for a high?efficiency solution even at light load conditions. vcc uvlo ensures the mosfets are off when supply voltages are low. a bi?directional enable pin provides a fault signal to the controller when a uvlo fault is detected. features ? space?efficient 3 mm x 3 mm dfn8 thermally?enhanced package ? vcc range of 4.5 v to 13.2 v ? integrated bootstrap diode ? 5 v 3?stage pwm input ? zero current detect function provides power saving operation during light load conditions ? bi?directional enable feature pulls enable pin low during a uvlo fault ? output disable control turns off both mosfets ? vcc undervoltage lockout ? adaptive anti?cross conduction circuit protects against cross?conduction during fet turn?on and turn?off ? direct interface to ncp6151 and other compatible pwm controllers ? thermally enhanced package ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? power solutions for notebook and desktop systems this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. device package shipping ? ordering information NCP81063mntxg dfn8 (pb?free) 3000 / tape & reel www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. dfn8 mn suffix case 506bj marking diagram 1 81063 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 81063 alyw 1 (note: microdot may be in either location)
NCP81063 www. onsemi.com 2 figure 1. pin diagram drvh sw gnd drvl bst pwm en vcc 1 flag (top view) 9 bst pwm logic drvh sw anti?cross conduction vcc drvl vcc en fault uvlo pre?ov zcd detection figure 2. block diagram table 1. pin descriptions pin no. symbol description 1 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2 pwm control input: pwm = high drvh is high, drvl is low. pwm = mid zero current detect enabled. diode emulation mode. pwm = low drvh is low, drvl is high. 3 en 3?state input: en = high driver is enabled. en = low driver is disabled. 4 vcc power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node (qfn flag). 7 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 8 drvh high side gate drive output. connect to the gate of high side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to ground plane.
NCP81063 www. onsemi.com 3 figure 3. application circuit vreg_sw1_hg vccp tp3 vreg_sw1_out vreg_sw1_lg tp6 tp7 tp8 tp4 tp1 tp2 tp5 ntmfs4851n ntmfs4851n q9 q10 ntmfs4821n q1 NCP81063 bst pwm en vcc hg sw gnd lg pad dron pwm csn11 csp11 c1 c2 c3 ce9 l r3 c6 r164 12v_power r1 r143 c4 0.027uf 0.0 1.02 c5 1uf r142 0.0 0.0 2.2 2700pf 235nh 4.7uf 4.7uf 4.7uf 390uf + jp13_etch jp14_etch table 2. absolute maximum ratings pin symbol pin name v max v min vcc main supply voltage input 15 v ?0.3 v bst bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 15 v wrt/ sw ?0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v 50 ns ?5 v ?10 v (200 ns) drvh high side driver output bst+0.3 v ?0.3 v wrt/sw ?2 v (<200 ns) wrt/sw drvl low side driver output vcc+0.3 v ?0.3 v dc ?5 v (<200 ns) pwm drvh and drvl control input 6.5 v ?0.3 v en enable pin 6.5 v ?0.3 v gnd ground 0 v 0 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. table 3. thermal information (all signals referenced to agnd unless noted otherwise) symbol parameter value unit r ja thermal characteristic (note 1) 74 c/w t j operating junction temperature range ?400 to 125 c t a operating ambient temperature range ?10 to +125 c t stg maximum storage temperature range ?55 to +150 c msl moisture sensitivity level 1 * the maximum package power dissipation must be observed. 1. i in 2 cu, 1 oz thickness.
NCP81063 www. onsemi.com 4 table 4. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter test conditions min. typ. max. units supply voltage vcc operation voltage 4.5 13.2 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv supply current normal mode icc + ibst, en = 5 v, pwm = osc, fsw = 100 khz, cload = 3 nf for drvh, 3 nf for drvl 10 ma standby current icc + ibst, en = gnd 0.5 1.4 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 2.0 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 2.0 ma bootstrap diode forward v oltage v cc = 12 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high 3.4 v pwm mid?state 1.3 2.7 v pwm input low 0.7 v zcd blanking timer 250 ns high side driver (vcc = 12 v) output impedance, sourcing current vbst ? vsw = 12 v 1.9 3.0 output impedance, sinking current vbst ? vsw = 12 v 1.0 1.7 drvh rise time tr drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 16 30 ns drvh fall time tf drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 11 25 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf 8.0 30 ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 30 ns sw pull down resistance sw to pgnd 37.5 k drvh pull down resistance drvh to sw, bst?sw = 0 v 37.55 k high side driver (vcc = 5 v) output impedance, sourcing current vbst ? vsw = 5 v 2.5 output impedance, sinking current vbst ? vsw = 5 v 1.6 drvh rise time tr drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 30 ns drvh fall time tf drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 27 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf 20 ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 27 ns sw pull down resistance sw to pgnd 37.5 k drvh pull down resistance drvh to sw, bst?sw = 0 v 37.5 k low side driver (vcc = 12 v) output impedance, sourcing current 2.0 3.0
NCP81063 www. onsemi.com 5 table 4. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter units max. typ. min. test conditions low side driver (vcc = 12 v) output impedance, sinking current 0.7 1.5 drvl rise time tr drvl c load = 3 nf 16 35 ns drvl fall time tf drvl c load = 3 nf 11 20 ns drvl turn?off propagation delay tpdl drvl c load = 3 nf 35 ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 8.0 30 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 37.5 k low side driver (vcc = 5 v) output impedance, sourcing current 2.5 output impedance, sinking current 1.0 drvl rise time tr drvl c load = 3 nf 30 ns drvl fall time tf drvl c load = 3 nf 22 ns drvl turn?off propagation delay tpdl drvl c load = 3 nf 27 ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 12 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 37.5 k en input input voltage high 2.0 v input voltage low 1.0 v hysteresis 500 mv normal mode bias current ?1 1 a enable pin sink current 4 30 ma propagation delay time 20 40 ns sw node sw node leakage current 20 a zero cross detection threshold v oltage sw to ?20 mv, ramp slowly until bg goes off (start in dcm mode) (note 2) ?3 mv table 5. decoder truth table pwm input zcd drvl drvh pwm high zcd reset low high pwm mid positive current through the inductor high low pwm mid zero current through the inductor low low pwm low zcd reset high low 2. guaranteed by design; not production tested.
NCP81063 www. onsemi.com 6 figure 4. figure 5. timing diagram pwm drvh?sw drvl il 1v 1v
NCP81063 www. onsemi.com 7 applications information the NCP81063 gate driver is a single?phase mosfet driver designed for driving n?channel mosfets in a synchronous buck converter topology. low?side driver the low?side driver is designed to drive a ground?referenced low?r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. high?side driver the high?side driver is designed to drive a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. when the NCP81063 is starting up, the sw pin is held at ground, allowing the bootstrap capacitor to charge up to vcc through the bootstrap diode. when the pwm input is driven high, the high?side driver will turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet is fully turned on, sw will settle to vin and bst will settle to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . power supply decoupling the NCP81063 can source and sink relatively large currents to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage, a low?esr capacitor should be placed near the vcc and gnd pins. a mlcc between 1 f and 4.7 f is typically used. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. once vcc reaches this threshold, the pwm signal will control drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh, drvl and sw to prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. bi?directional en signal the enable pin (en) is used to disable the drvh and drvl outputs to prevent power transfer. when en is above the en hi threshold, drvh and drvl change their states according to the pwm input. a uvlo fault turns on the internal mosfet that pulls the en pin towards ground. by connecting en to the dron pin of a controller, the controller is alerted when the driver encounters a fault condition. three?state pwm input switching pwm between logic?high and logic?low states will allow the driver to operate in continuous conduction mode as long as vcc is greater than the uvlo threshold and en is high. the threshold limits are specified in the electrical characteristics table in this datasheet. refer to figure 21 for the gate timing diagrams and table 1 for the en/pwm logic table. when pwm is set above pwm hi , drvl will first turn off after a propagation delay of tpdl drvl . to ensure non?overlap between drvl and drvh, there is a delay of tpdh drvh from the time drvl falls to 1 v, before drvh is allowed to turn on. when pwm falls below pwm lo , drvh will first turn off after a propagation delay of tpdl drvh . to ensure non?overlap between drvh and drvl, there is a delay of tpdh drvl from the time drvh ? sw falls to 1 v, before drvl is allowed to turn on. when pwm enters the mid?state voltage range, pwm mid , drvl goes high after the non?overlap delay, and stays high for the duration of the zcd blanking timer and an 80 ns de?bounce timer. once these timers expire, sw is monitored for zero current detection and pulls drvl low once zero current is detected. thermal considerations as power in the NCP81063 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the NCP81063 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the NCP81063 can handle is given by: p d(max) t j(max) t a r ja (eq. 1) since t j is not recommended to exceed 150 c, the NCP81063, soldered on to a 645 mm 2 copper area, using 1 oz. copper and fr4, can dissipate up to 2.3 w when the ambient temperature (t a ) is 25 c. the power dissipated by the NCP81063 can be calculated from the following equation: p d vcc n hs qg hs n ls qg ls f i standby (eq. 2) where n hs and n ls are the number of high?side and low?side fets, respectively, qg hs and qg ls are the gate charges of the high?side and low?side fets, respectively and f is the switching frequency of the converter.
NCP81063 www. onsemi.com 8 package dimensions dfn8 3x3, 0.5p case 506bj issue o ??? ??? ??? soldermask defined pin 1 reference a b c 0.10 2x 2x top view d e c 0.10 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e2 bottom view b 0.10 8x l 14 0.05 c ab c d2 e k 85 8x 8x (a3) c c 0.05 8x c 0.05 side view a1 a seating plane dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.64 1.84 e 3.00 bsc e2 1.35 1.55 e 0.50 bsc k 0.20 ??? l 0.30 0.50 note 3 l detail a optional construction l1 detail a 0.00 0.03 note 4 detail b 3.30 8x dimension: millimeters 0.63 1.55 1.85 0.50 pitch 8x 0.35 mounting footprint detail a on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates , and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea th associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semicon ductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81063/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative
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